The present invention relates to high-speed serial data transceivers and, in particular, high-speed data serializers.
Serial data communication circuits use data serializers for converting a plurality of parallel data inputs to a single serial data stream. A typical data serializer includes a time-division data multiplexer, which sequentially multiplexes the parallel data outputs to a single output. The sequential selection of data inputs is controlled by a clock circuit which has two or more phases. A typical multi-phase clock circuit generates n select clock signals. The n select clock signals are equally distributed in phase over 360 degrees. The select clock signals are used to select individual data inputs in a particular order.
A given high speed data serializer is more valuable if it can be adapted for different applications, and in particular for different data rates. But different data rates can have different slew rate requirements. It is therefore desirable to be able to use the same data serializer for different applications (i.e., at different data rates) and also to adjust the slew rate of the serializer for each application. Existing approaches for adjusting the slew rate often use feedback techniques. A buffer""s output slew rate is monitored and, through feedback, the signal at the input to the buffer is controlled so as to achieve the desired output slew rate. However, to ensure stable operation, the bandwidth and/or the gain of the feedback loop must be limited. The result is an imperfect slew rate control. Another problem is that the devices connected to the output signal whose slew rate is being monitored (so as to control its slew rate) are susceptible to damage from electrostatic discharge.
A data serializer having improved slew rate control is desired.
A data serializer according to one embodiment of the present invention includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n data inputs and n is an integer greater than one. Each pair of first and second control inputs is driven by a respective logic AND circuit having a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source.
One aspect of the present invention is directed to a data serializer, which includes n data inputs, n clock inputs, a differential output stage and an input stage. Each clock input is out of phase with the other clock inputs and corresponds to one of the n data inputs. The differential output stage has first and second differential data outputs and n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of the n data inputs. The input stage includes, for each of the n data inputs, a first logic AND circuit and a second logic AND circuit The first logic AND circuit has first, second and third inputs coupled to the data input, the corresponding clock input and an inverse of the clock input that next trails the corresponding clock input in phase, respectively, and has an output which is coupled to the first control input of the corresponding pair of control inputs. The output of the first logic AND gate has a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source. The second logic AND gate circuit has first, second and third inputs coupled to an inverse of the data input, the corresponding clock input and the inverse of the clock input that next trails the corresponding clock input in phase, respectively, and an output which is coupled to the second control input of the corresponding pair of control inputs. The output of the second logic AND gate has a rise time controlled by the first adjustable controlled current source and a fall time controlled by the second adjustable controlled current source.
Another aspect of the present invention is directed to a method of serializing a parallel data input having n data inputs. The method includes providing n differential transistor pairs in parallel with one another, between first and second differential data outputs and a tail current source. Each transistor pair has a respective pair of first and second control inputs. The method further includes receiving the n data inputs and n clock signals, wherein each clock signal is out of phase with the other clock signals and corresponds to one of the n data inputs. For each of the n data inputs received, the respective pair of first and second control inputs is driven between first and second voltage levels with a rise time controlled by a first adjustable controlled current source and a fall time controlled by a second adjustable controlled current source, based on logic states of the corresponding data input, the corresponding clock signal and the clock signal that next trails the corresponding clock signal in phase.